Paul Lassa Email & Phone Number
ASIC Development Lead @ Applied Brain Research
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Paul Lassa Location
- California, United States
Paul Lassa Work
- ASIC Development Lead @ (January 2025 - Present)
- Principal Engr., SSD, Storage Design Consulting, Mobile App Design and Development @ ICH (January 2013 - Present)
- Chief Product Officer @ (January 2017 - January 2018)
- Advisor, Engineering Liaison @ (January 2015 - January 2017)
- Sr. Manager, System Design Engineering, Consumer, Client SATA, PCIe SSD, USB, CF Product Development @ (January 2010 - January 2012)
- Principal Engr., SSD Architecture Group (SATA SSD, ONFI scalable architecture) @ (January 2009 - January 2010)
- Sr. Manager, ASIC and FPGA Design Engineering (SATA and PCIe, ONFI, USB, SD and MMC, MS, CF and ATA) @ (January 2007 - January 2009)
- Sr. Manager, ASIC Design Engineering, Flash Storage controllers (USB, SD and MMC, MS) @ (January 2006 - January 2007)
- ASIC Design Manager II, Flash Storage controllers (USB, SD and MMC, MS, Crypto) @ (January 2005 - January 2006)
- ASIC Design Manager, USB Flash drives @ (January 2003 - January 2005)
- Sr. ASIC and Sys. SW Engineer @ TLA (January 2000 - January 2003)
- Sr. R and D Engineer, Hardware Engineering @ (January 1996 - January 1999)
- Sr. ASIC and FPGA Design Engineer @ (January 1994 - January 1996)
- Sr. Hardware Project Engineer – LED ImageWall Display @ MagicVideo Technology (January 1993 - January 1994)
- Sr. Engineer, ASIC Design, PCB Hardware Design @ (January 1988 - January 1993)
- Software Engineer @ Timeworks, Inc. (January 1982 - January 1984)
Paul Lassa Education
- Stanford University
MS (Electrical & Computer Engineering)
2000 - University of Illinois Urbana-Champaign
BS (Electrical & Computer Engineering)
1988
Paul Lassa Skills
- Systems Design
- NAND Flash
- Program Management
- Integration
- Linux
- Design
- Mobile Applications
- Nand
- Software Development
- Management
- Cross Functional Team Leadership
- Development
- Semiconductors
- RTOS
- System Design
- Functional Verification
- Static Timing Analysis
- Computer Architecture
- ARM
- PCB design
- Cloud Computing
- Xcode
- SATA
- Sales
- SSD
- Microsoft Excel
- C++
- Software Engineering
- Algorithms
- Hardware Architecture
- PCIe
- Continuous Integration
- FPGA
- Debugging
- Firmware
- Embedded Software
- Project Management
- Performance Analysis
- Flash Memory
- Swift
- Hardware
- iOS development
- System Architecture
- Device Drivers
- Storage
- Engineering Management
- Object Oriented Design
- Team Leadership
- Mixed Signal
- Strategic Planning
- Microsoft Office
- Android
- Embedded Systems
- USB
- ASIC
- Python
- VLSI
- Patents
- SoC
- Solutions
- Verilog
- Blockchain
- Leadership
- Requirements Analysis
- System on a Chip
- Integrated Circuits
- Matlab
- C (Programming Language
- Electrical Engineering
- Simulations
- Product Development
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Paul Lassa Summary
- Paul Lassa, based in California, United States, is currently a ASIC Development Lead at Applied Brain Research. Paul Lassa brings experience from previous roles at ICH, Friend Software Corporation AS and SanDisk. Paul Lassa holds a MS in Electrical & Computer Engineering @ Stanford University. With a robust skill set that includes Systems Design, NAND Flash, Program Management, Integration, Linux and more. Paul Lassa has 2 emails on RocketReach.
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