Paul Everhardt Email & Phone Number
Director, ASIC Physical Design @ Chelsio Communications
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Paul Everhardt Location
- Sunnyvale, CA, US
Paul Everhardt Work
- Director, ASIC Physical Design @ (June 2001 - Present)
- Engineering Manager @ (August 1992 - June 2001)
- Design Engineer @ (September 1985 - July 1992)
Paul Everhardt Education
- Stanford University
MS (Electrical Engineering)
1984-1985 - University of Illinois Urbana-Champaign
BS (Computer Engineering)
1980-1984
Paul Everhardt Skills
- Engineering Management
- Hands-on Technical Leadership
- Ethernet
- 10G Ethernet
- PCIe
- SERDES
- DDR3
- Semiconductors
- Integrated Circuit Design
- VLSI
- Hardware Bring-up
- Silicon Validation
- Networking
- Computer Architecture
- High-speed Digital Design
- Signal Integrity
- RTL design
- Verilog
- Logic Synthesis
- Static Timing Analysis
- Timing Closure
- Equivalence Checking
- Power Estimation
- Power Optimization
- DFT
- BIST
- JTAG
- Boundary Scan
- Floorplanning
- EDA
- Perl
- TCL
- Primetime
- Conformal LEC
- 45nm
- 65nm
- Design
- Photoshop
- Hardware Engineers
- Hands on Technical
- Marketing
- High Speed Digital Design
- ASIC
- Integrated Circuit
- Web Design
- Hands on Technical Leadership
- High Speed Digital
- Graphic Design
- Physical Design
- Illustrator
Paul Everhardt Summary
- Paul Everhardt, based in Sunnyvale, CA, US, is currently a Director, ASIC Physical Design at Chelsio Communications. Paul Everhardt brings experience from previous roles at Silicon Graphics and Tandem Computers. Paul Everhardt holds a 1984 - 1985 MS in Electrical Engineering @ Stanford University. With a robust skill set that includes Engineering Management, Hands-on Technical Leadership, Ethernet, 10G Ethernet, PCIe and more. Paul Everhardt has 1 emails on RocketReach.
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Paul Everhardt
Director, ASIC Physical Design
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