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Pat Ridenour Location
Bethlehem, PA, US
Pat Ridenour Work
Analog and Digital Layout Designer @
Physical Designer @ Lattice Semiconductor (January 2000 - January 2011)
Pat Ridenour Skills
DRC
LVS
Floorplanning
Physical Verification
Timing Closure
Physical Design
Radiation Hardened Layout
IR drop analysis
ASIC
CMOS
Debugging
EDA
IC
Mixed Signal
Semiconductors
SoC
Static Timing Analysis
Verilog
IR
Drop Analysis
Ir Drop Analysis
Pat Ridenour Summary
Pat Ridenour, based in Bethlehem, PA, US, is currently a Analog and Digital Layout Designer at Lattice Semiconductor. Pat Ridenour brings experience from previous roles at Lattice Semiconductor. With a robust skill set that includes DRC, LVS, Floorplanning, Physical Verification, Timing Closure and more. Pat Ridenour has 2 emails and 1 mobile phone numbers on RocketReach.
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