Pat Liston Email & Phone Number
SRAM Memory Compiler Methodology Manager @ Intel Corporation
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Pat Liston Location
- Austin, TX, US
Pat Liston Work
- 2012 -now SRAM Memory Compiler Methodology Manager @
- 2008 -2012 L and M SRAM Design Manager @
- 2006 -2008 SRAM Design Manager @
- 2000 -2006 Custom SRAM Designer @
- 1991 -2000 Failure Analyst @
- 1989 -1991 Product Engineer @
Pat Liston Education
- Texas A&M University
BSEE
1984-1988
Pat Liston Skills
- SRAM
- Engineering Management
- Electrical Engineering
- ROM
- Failure Analysis
- Semiconductor Design
- CMOS
- IC
- VLSI
- ASIC
- ARM
- Digital Signal Processors
- Mixed Signal
- Semiconductor Industry
- Semiconductors
- SoC
- Analog
- Debugging
- Testing
- EDA
- DRC
- Silicon
- Memory Test
- Yield
- Physical Design
- Integrated Circuit Design
- Memory
- Compiler Construction
- Engineering
- Leadership
- Business Analysis
Pat Liston Summary
- Pat Liston, based in Austin, TX, US, is currently a SRAM Memory Compiler Methodology Manager at Intel Corporation. Pat Liston brings experience from previous roles at Freescale Semiconductor and Motorola. Pat Liston holds a 1984 - 1988 BSEE @ Texas A&M University. With a robust skill set that includes SRAM, Engineering Management, Electrical Engineering, ROM, Failure Analysis and more. Pat Liston has 3 emails and 1 mobile phone numbers on RocketReach.
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