Pat Liston Email & Phone Number
SRAM Memory Compiler Methodology Manager @ Intel Corporation
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Pat Liston Location
- Austin, TX, US
Pat Liston Work
- SRAM Memory Compiler Methodology Manager @ (August 2012 - Present)
- L and M SRAM Design Manager @ (January 2008 - August 2012)
- SRAM Design Manager @ (January 2006 - January 2008)
- Custom SRAM Designer @ (January 2000 - January 2006)
- Failure Analyst @ (January 1991 - January 2000)
- Product Engineer @ (January 1989 - January 1991)
Pat Liston Education
- Texas A&M University
BSEE
1984-1988
Pat Liston Skills
- ARM
- ASIC
- Analog
- CMOS
- DRC
- Debugging
- Digital Signal Processors
- EDA
- Electrical Engineering
- Engineering Management
- Failure Analysis
- IC
- Integrated Circuit Design
- Memory Test
- Mixed Signal
- Physical Design
- ROM
- SRAM
- Semiconductor Design
- Semiconductor Industry
- Semiconductors
- Silicon
- SoC
- Testing
- VLSI
- Yield
- Memory
- Compiler Construction
- Engineering
- Leadership
- Business Analysis
Pat Liston Summary
- Pat Liston, based in Austin, TX, US, is currently a SRAM Memory Compiler Methodology Manager at Intel Corporation. Pat Liston brings experience from previous roles at Freescale Semiconductor and Motorola. Pat Liston holds a 1984 - 1988 BSEE @ Texas A&M University. With a robust skill set that includes ARM, ASIC, Analog, CMOS, DRC and more. Pat Liston has 3 emails and 1 mobile phone numbers on RocketReach.
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