Pascal Boudreau Email
Senior ASIC and FPGA Designer @ Hardent
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Pascal Boudreau Location
- Sainte-Julie, QC, CA
Pascal Boudreau Work
- FPGA Design and Verification Expert @ (March 2018 - October 2023)
- Design and Verification Consulting Expert for ASIC and FPGA @ (March 2016 - March 2018)
- Senior ASIC and FPGA Designer @
- Design and Verification Consulting Expert for ASIC and FPGA @ (January 2012 - February 2016)
- ASIC Designer @
- ASIC and FPGA Designer and Verification @
- Senior ASIC and FPGA Designer @ (January 2006 - January 2012)
- ASIC Designer @ (January 1999 - January 2005)
- Design and Verification Consulting Expert for ASIC and FPGA @
- ASIC and FPGA Designer and Verification @ (January 1997 - January 1998)
Pascal Boudreau Education
- Université de Sherbrooke
Bachelor's degree (Electrical and Electronics Engineering)
1995-1999
Pascal Boudreau Skills
- FPGA
- RTL design
- VHDL
- ASIC
- Verilog
- ModelSim
- Xilinx
- Altera
- SystemVerilog
- SoC
- Functional Verification
- TCL
- Static Timing Analysis
- EDA
- RTL coding
- Timing Closure
- NCSim
- Primetime
- UVM
- Telecommunications
- Verification
Pascal Boudreau Summary
- Pascal Boudreau, based in Sainte-Julie, QC, CA, is currently a Senior ASIC and FPGA Designer at Hardent. Pascal Boudreau brings experience from previous roles at Accedian, Hardent, Orthogone Technologies and PMC-Sierra. Pascal Boudreau holds a 1995 - 1999 Bachelor's degree in Electrical and Electronics Engineering @ Université de Sherbrooke. With a robust skill set that includes FPGA, RTL design, VHDL, ASIC, Verilog and more.
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