Parv Sharma Email & Phone Number
Circuit Design Engineer @ Intel Corporation
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Parv Sharma Location
- Hillsboro, OR, US
Parv Sharma Work
- 2020 -now Circuit Design Engineer @
- 2017 -2020 Library Design Engineer @
- 2016 -2017 Research Assistant @
- 2012 -2012 Trainee @
Parv Sharma Education
- Arizona State University 2014-2016
- Vellore Institute of Technology 2010-2014
Parv Sharma Skills
- Cadence Virtuoso
- Layout Design
- Assembly Language
- Synopsys Modal Compiler
- RTL design
- Matlab
- Photoshop
- ASIC
- Perl Automation
- Xilinx ISE
- Verilog
- Microcontrollers
- Photography
- Xilinx
- Cadence
- Strategic Planning
- Data Structures
- Programming
- Microsoft Excel
- Keil
- C++
- Stateflow
- Python
- SystemVerilog
- Solidworks
- Simulink
Parv Sharma Summary
- Parv Sharma, based in Hillsboro, OR, US, is currently a Circuit Design Engineer at Intel Corporation. Parv Sharma brings experience from previous roles at Intel Corporation, Arizona State University and HCL Infosystems Ltd. Parv Sharma holds a 2014 - 2016 Arizona State University. With a robust skill set that includes Cadence Virtuoso, Layout Design, Assembly Language, Synopsys Modal Compiler, RTL design and more. Parv Sharma has 5 emails and 2 mobile phone numbers on RocketReach.
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