Parul Agarwal Email & Phone Number
Sr. Digital Design and Integration Lead @ PsiQuantum
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Parul Agarwal Location
- San Jose, CA, US
Parul Agarwal Work
- Sr. Digital Design and Integration Lead @ (September 2021 - Present)
- SoC Design Engineer @ (December 2016 - September 2021)
- Senior Design Engineer @ (July 2014 - December 2016)
- Project Lead @ (July 2011 - March 2013)
- Tech. Lead @ (October 2010 - June 2011)
- Senior Design Engineer @ (October 2006 - September 2010)
- Design Engineer @ (June 2004 - September 2006)
Parul Agarwal Education
- Coleman College
Masters (Management)
2014-2015 - Mahatma Jyotiba Phule (MJP) Rohilkhand University
(Communication, Electronics)
1999-2003 - Sacred Heart Convent Senior Secondary School, Mathura
(English)
1996-1997 - St. Paul's School
(English, Hindi)
1994-1995
Parul Agarwal Skills
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- Debugging
- ECO Handling
- EDA
- Embedded Systems
- Equivalence Checking
- Formal Verification
- Functional Verification
- IC
- Integrated Circuit Design
- Integrated Circuits (IC)
- Logic Synthesis
- Perl
- Primetime
- RTL Coding
- RTL Design
- Semiconductors
- SoC
- Soc Integration
- Static Timing Analysis
- System on a Chip (SoC)
- SystemVerilog
- VHDL
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
Parul Agarwal Summary
- Parul Agarwal, based in San Jose, CA, US, is currently a Sr. Digital Design and Integration Lead at PsiQuantum. Parul Agarwal brings experience from previous roles at Intel Corporation, Collabera Inc., Atrenta and STMicroelectronics Pvt Ltd. Parul Agarwal holds a 2014 - 2015 Masters in Management @ Coleman College. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), Debugging, ECO Handling, EDA and more. Parul Agarwal has 2 emails on RocketReach.
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