Parthee Patel's Location
Folsom, CA, US
Parthee Patel's Work
- Graphics Hardware Engineer @ Intel Corporation
- Validation Intern @ Intel Corporation
- Component Design Engineer Intern USB 3.0 @ Intel Corporation
Parthee Patel's Education
- California State University-Sacramento
Master of Science (M.S.) (Electrical and Electronics Engineering)
2012 - 2014
Parthee Patel's Skills
- Verilog
- VLSI
- Computer Architecture
- Logic Synthesis
- VHDL
- Logic Design
- RTL design
- C
- TCL
- Synopsys tools
Parthee Patel's Summary
Parthee Patel, based in Folsom, CA, US, is currently a Graphics Hardware Engineer at Intel Corporation, bringing experience from previous roles at Intel Corporation. Parthee Patel holds a 2012 - 2014 Master of Science (M.S.) in Electrical and Electronics Engineering @ California State University-Sacramento. With a robust skill set that includes Verilog, VLSI, Computer Architecture, Logic Synthesis, VHDL and more, Parthee Patel contributes valuable insights to the industry. Parthee Patel has 2 emails and 1 mobile phone number on RocketReach.
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