Paras Arora Email & Phone Number
ASIC Design Engineer @ Apple
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Paras Arora Location
- Cupertino, CA, US
Paras Arora Work
- 2020 -now ASIC Design Engineer @
- 2019 -2019 Intern @
- 2014 -2018 Senior Design Engineer @
- 2013 -2013 Analog Applications Associate (Intern) @
Paras Arora Education
- Texas A&M University
Master of Science - MS (Computer Engineering)
2018-2020 - NIT Kurukshetra
Bachelor of Technology (B.Tech.) (Electrical, Electronics and Communications Engineering)
2010-2014 - The Heritage School, Dehradun
Paras Arora Summary
- Paras Arora, based in Cupertino, CA, US, is currently a ASIC Design Engineer at Apple. Paras Arora brings experience from previous roles at Arm, NXP acquires Freescale Semiconductor and Texas Instruments. Paras Arora holds a 2018 - 2020 Master of Science - MS in Computer Engineering @ Texas A&M University. Paras Arora has 4 emails and 3 mobile phone numbers on RocketReach.
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