Parag Rao's Location
San Jose, CA, US
Parag Rao's Work
- Design Verification, Next-Gen CPU @ Google
- MTS Verification Engineer @ AMD
- Senior Verification Engineer @ AMD
- Senior Design Verification Engineer- II @ Xilinx
- Senior Design Verification Engineer - I @ Xilinx
- Staff Verification Engineer @ Cypress Semiconductor Corporation
- IC Design Verification Engineer @ Atmel Corporation
- Junior Design Engineer @ Arasan Chip Systems Inc.
- Math Workshop Facilitator @ San Jose State University
- Embedded Hardware Engineer @ Selec Controls Pvt. Ltd.
Parag Rao's Education
- San Jose State University
M.S in Electrical Engineering (Digital VLSI)
2013 - 2015 - University of Mumbai
Bachelor of Engineering (BE) (Electrical and Electronics Engineering)
2008 - 2012
Parag Rao's Skills
- VLSI
- Embedded Systems
- Verilog
- Hardware Architecture
- Automation
- C++
- Cadence Virtuoso
- SystemVerilog
- Perl Script
- ASIC
Parag Rao's Summary
Parag Rao, based in San Jose, CA, US, is currently a Design Verification, Next-Gen CPU at Google, bringing experience from previous roles at AMD and Xilinx. Parag Rao holds a 2013 - 2015 M.S in Electrical Engineering in Digital VLSI @ San Jose State University. With a robust skill set that includes VLSI, Embedded Systems, Verilog, Hardware Architecture, Automation and more, Parag Rao contributes valuable insights to the industry. Parag Rao has 2 emails on RocketReach.
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