Pankil Patel Location
Los Gatos, CA, US
Pankil Patel Work
- 2022 - now Director, SOC Design and Implementation @ Rapid Silicon
- 2018 - 2022 Sr. Principal ASIC Design Engineer @ onsemi
- 2014 - 2018 Principal Application Engineer @ Cadence Design Systems
- 2012 - 2014 Asic Design Verification Engineer @ Marvell India
- 2011 - 2012 Intern ASIC Engineer @ LSI, an Avago Technologies Company
- 2011 - 2012 Intern ASIC Characterization Engineer @ SanDisk®
- 2009 - 2011 System Engineer @ MCE Inc. San Jose
- 2008 - 2009 OCP @ AIESEC
Pankil Patel Education
- Santa Clara University
Master (Electrical Engiineering)
2009 - 2011 - Gujarat University
BS (Electronics and Communication)
2005 - 2009
Pankil Patel Skills
- Verilog
- ASIC
- Debugging
- RTL Design
- Formal Verification
- Low-power Design
- C++
- C
- Engineering
- AES
Pankil Patel Summary
Pankil Patel, based in Los Gatos, CA, US, is currently a Director, SOC Design and Implementation at Rapid Silicon. Pankil Patel brings experience from previous roles at onsemi, Cadence Design Systems, Marvell Semiconductor and LSI, an Avago Technologies Company. Pankil Patel holds a 2009 - 2011 Master in Electrical Engiineering @ Santa Clara University. With a robust skill set that includes Verilog, ASIC, Debugging, RTL Design, Formal Verification and more. Pankil Patel has 3 emails and 1 mobile phone numbers on RocketReach.
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