Pankil Patel Email & Phone Number
SOC Design Integration Lead @ Lumotive
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Pankil Patel Location
- California, United States
Pankil Patel Work
- SOC Design Integration Lead @ (December 2023 - Present)
- Director, SOC Design and Implementation @ (November 2022 - August 2024)
- Sr. Principal ASIC Design Engineer @ (August 2018 - November 2022)
- Principal Application Engineer @ (July 2014 - August 2018)
- Asic Design Verification Engineer @ (January 2012 - July 2014)
- Intern ASIC Engineer @ (May 2011 - January 2012)
- Intern ASIC Characterization Engineer @ (April 2011 - January 2012)
- System Engineer @ MCE Inc. San Jose (December 2009 - April 2011)
- OCP @ (January 2008 - January 2009)
Pankil Patel Education
- Santa Clara University
Master (Electrical Engiineering)
2009-2011 - Gujarat University
BS (Electronics and Communication)
2005-2009
Pankil Patel Skills
- Verilog
- ASIC
- Debugging
- RTL Design
- Formal Verification
- Low-power Design
- C++
- C
- Engineering
- AES
- SQL
- Trading
- Management
- Business Analysis
- Low Power Design
- SAN
- Photoshop
- Testing
- Application Specific Integrated Circuits Asic
- Application Specific Integrated Circuits
Pankil Patel Summary
- Pankil Patel, based in California, United States, is currently a SOC Design Integration Lead at Lumotive. Pankil Patel brings experience from previous roles at Rapid Silicon, onsemi, Cadence Design Systems and Marvell Semiconductor. Pankil Patel holds a 2009 - 2011 Master in Electrical Engiineering @ Santa Clara University. With a robust skill set that includes Verilog, ASIC, Debugging, RTL Design, Formal Verification and more. Pankil Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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