Padma P Email
Lead Engineer @ Aricent
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Padma P Location
- Austin, TX, US
Padma P Work
- Lead Engineer @ (December 2012 - Present)
- Senior Design Engineer @ (January 2011 - December 2012)
- Design Engineer @ (January 2007 - January 2011)
- Design Engineer @ (August 2004 - January 2007)
Padma P Education
- Manipal University
Master Of Science
2003-2005 - Madurai Kamaraj University 1997-2001
Padma P Skills
- Physical Design , place and route , Floorplanning, power planning, clock tree synthesis , Route, STA, Timing, Low power analysis , EMIR analysis, Physical verification , DRC , LVS
- Physical design
- Static Timing Analysis
- Timing Closure
- VLSI
- ASIC
- Primetime
- SoC
- Physical Verification
- DRC
- RTL design
- Verilog
- LVS
- SystemVerilog
- Functional Verification
- Floorplanning
- EDA
- Low-power Design
- TCL
- Low Power Design
Padma P Summary
- Padma P, based in Austin, TX, US, is currently a Lead Engineer at Aricent. Padma P brings experience from previous roles at Amd, Arm and Sasken Communication Technologies. Padma P holds a 2003 - 2005 Master Of Science @ Manipal University. With a robust skill set that includes Physical Design , place and route , Floorplanning, power planning, clock tree synthesis , Route, STA, Timing, Low power analysis , EMIR analysis, Physical verification , DRC , LVS, Physical design, Static Timing Analysis, Timing Closure, VLSI and more. Padma P has 2 emails on RocketReach.
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