Pablo Tapia Reyero's Location
Madrid, ES
Pablo Tapia Reyero's Work
- ASIC Design Engineer @ KDPOF, Knowledge Development for POF, SL
- ASIC Design Engineer @ SIDSA
- Electronic Systems Engineer @ Indra
- R and D scholarship @ Institute for Systems based on Optoelectronics and Microtechnology
Pablo Tapia Reyero's Education
- Universidad Politécnica de Madrid
Ingeniero Superior de Telecomunicaciones (Electrónica)
2001 - 2006
Pablo Tapia Reyero's Skills
- Matlab
- Simulaciones
- Circuito Integrado De
- ASIC
- Procesador Digital De
- Linux
- FPGA
- Circuito Impreso
- VHDL
- C
Pablo Tapia Reyero's Summary
Pablo Tapia Reyero, based in Madrid, ES, is currently a ASIC Design Engineer at KDPOF, bringing experience from previous roles at SIDSA, Indra and Institute for Systems based on Optoelectronics and Microtechnology. Pablo Tapia Reyero holds a 2001 - 2006 Ingeniero Superior de Telecomunicaciones in Electrónica @ Universidad Politécnica de Madrid. With a robust skill set that includes Matlab, Simulaciones, Circuito Integrado De, ASIC, Procesador Digital De and more, Pablo Tapia Reyero contributes valuable insights to the industry. Pablo Tapia Reyero has 1 email on RocketReach.
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Madrid, Madrid, Spain2
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