Pablo Royer Email
IC Design - Memory @ STMicroelectronics
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Pablo Royer Location
- Grenoble, Auvergne-Rhône-Alpes, FR
Pablo Royer Work
- 2017 -now IC Design - Memory @
- 2016 -2017 PostDoc @
- 2015 -2016 Electronic Engineer, ASIC @
- 2011 -2015 PHD Candidate @
- 2012 -2013 Visiting PHD Student @
- 2011 -2012 Visiting PHD Student @
- 2010 -2011 Electronic Engineer, FPGA, DSP @
- 2009 -2010 Electronic Engineer, FPGA @
Pablo Royer Education
- Universidad Politécnica de Madrid
Master’s Degree (Electronic Systems Engineering)
2010-2011 - Universidad Politécnica de Madrid
Engineer’s Degree (Telecommunications Engineering)
2004-2009
Pablo Royer Skills
- Cadence Virtuoso
- Cadence Virtuoso Layout Editor
- Cadence SKILL
- ASIC
- Digital Circuit Design
- Cadence Spectre
- SPICE
- LaTeX
- Simulations
- Science
- Signal Processing
- Cadence Encounter
- Synopsys tools
- FinFET
- Matlab
- ModelSim
- FPGA
- Electronics
- Python
Pablo Royer Summary
- Pablo Royer, based in Grenoble, Auvergne-Rhône-Alpes, FR, is currently a IC Design - Memory at STMicroelectronics. Pablo Royer brings experience from previous roles at CEA-Leti, Universidad Politécnica de Madrid and imec. Pablo Royer holds a 2010 - 2011 Master’s Degree in Electronic Systems Engineering @ Universidad Politécnica de Madrid. With a robust skill set that includes Cadence Virtuoso, Cadence Virtuoso Layout Editor, Cadence SKILL, ASIC, Digital Circuit Design and more. Pablo Royer has 1 emails on RocketReach.
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