Pabbitha Rao Email
Design Verification Engineer @ VEDA IIT
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Pabbitha Rao Location
- Visakhapatnam, AP, IN
Pabbitha Rao Work
- 2024 -now Design Verification Engineer @
- 2023 -2023 Design Verification Engineer Trainee @
Pabbitha Rao Education
- University College of Engineering, Vizianagaram
Bachelor of Technology - BTech (Electronics And Communication)
2019-2023 - Narayana Junior College - India
Intermediate (MPC)
2017-2019 - Pereira English Noble School 2009-2017
Pabbitha Rao Skills
- Universal Verification Methodology (UVM)
- Assembly Language
- SystemVerilog
- Verilog
- Digital Circuit Design
- TCL
- Perl
- Unix
- C++
- C (Programming Language)
- HTML
- Cascading Style Sheets (CSS)
Pabbitha Rao Summary
- Pabbitha Rao, based in Visakhapatnam, AP, IN, is currently a Design Verification Engineer at VEDA IIT. Pabbitha Rao brings experience from previous roles at VEDA IIT. Pabbitha Rao holds a 2019 - 2023 Bachelor of Technology - BTech in Electronics And Communication @ University College of Engineering, Vizianagaram. With a robust skill set that includes Universal Verification Methodology (UVM), Assembly Language, SystemVerilog, Verilog, Digital Circuit Design and more.
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