P Tata Location
- India
P Tata Work
- 2026 -now Senior Staff Engineer @
- 2022 -2026 Senior Physical Design Engineer @
- 2019 -2022 Architect @
- 2018 -2019 Physical design Lead Engineer @
- 2016 -2018 Senior Physical Design Engineer @
- 2012 -2016 Senior Physical Design Engineer @
- 2012 -2012 Physical Design Trainee @ VEDA IIT
P Tata Education
- Birla Institute of Technology and Science, Pilani
Master of Technology - MTech (micro electronics)
2017-2019 - Narayana Engineering College
Bachelor’s Degree (Electronics and Communications Engineering)
2007-2011 - Narayana Junior College
Intermediate (MPC)
2005-2007 - Viswam High School
High School (SSC)
2004-2005
P Tata Skills
- VLSI
- Physical Design
- Static Timing Analysis
- Clock Tree Synthesis
- Physical Verification
- IO and Bump Planning
- Perl
- TCL
- Sed
- Awk
- C
- Verilog
- Embedded Systems
- SystemVerilog
- EDA
- Application-Specific Integrated Circuits (ASIC)
- Linux
- Semiconductors
P Tata Summary
- P Tata, based in India, is currently a Senior Staff Engineer at SEMIFIVE. P Tata brings experience from previous roles at Intel Corporation, Wipro and Sankalp Semiconductor. P Tata holds a 2017 - 2019 Master of Technology - MTech in micro electronics @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes VLSI, Physical Design, Static Timing Analysis, Clock Tree Synthesis, Physical Verification and more. P Tata has 1 emails on RocketReach.
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