Niravkumar Patel Email & Phone Number
Design Verification Engineer @ AMD
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Niravkumar Patel Location
- Chandler, AZ, US
Niravkumar Patel Work
- Design Verification Engineer @ (April 2026 - Present)
- Design Verification Engineer @ (August 2024 - April 2026)
- Design Verification Engineer @ (November 2019 - August 2024)
- Design Engineer @ (October 2015 - November 2019)
- Design Engineer @ (April 2012 - October 2015)
- Student Assistant @ (September 2008 - December 2008)
- Intern @ Twin Antenna (January 2007 - May 2007)
Niravkumar Patel Education
- San José State University
Master of Science (MS) (Electrical Engineer)
2008-2010 - Hemchandracharya North Gujarat University
Bachelor of Engineering - BE (Electronics & Communication)
2003-2007
Niravkumar Patel Skills
- AMS
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- Cadence Virtuoso
- Debugging
- Functional Verification
- Hardware Architecture
- Hardware Verification
- IP integration
- IP interation
- MSV
- ModelSim
- Problem Solving
- RTL Design
- RTL Verification
- RTL coding
- Semiconductor Engineering
- SoC
- Static Timing Analysis
- System on a Chip (SoC)
- SystemVerilog
- SystemVerilog, UVM, OVM, Verification, Test Plan, Random Constraint,
- Universal Verification Methodology (UVM)
- VHDL
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- Very Large Scale Integration Vlsi
- System On A Chip Soc
- Very Large Scale Integration
- System on a Chip
Niravkumar Patel Summary
- Niravkumar Patel, based in Chandler, AZ, US, is currently a Design Verification Engineer at AMD. Niravkumar Patel brings experience from previous roles at HCLTech, Intel Corporation and Microchip Technology. Niravkumar Patel holds a 2008 - 2010 Master of Science (MS) in Electrical Engineer @ San José State University. With a robust skill set that includes AMS, Application-Specific Integrated Circuits (ASIC), C, C++, Cadence Virtuoso and more. Niravkumar Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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