Niravkumar Patel Email & Phone Number
Design Verification Engineer @ AMD
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Niravkumar Patel Location
- Chandler, AZ, US
Niravkumar Patel Work
- 2026 -now Design Verification Engineer @
- 2024 -2026 Design Verification Engineer @
- 2019 -2024 Design Verification Engineer @
- 2015 -2019 Design Engineer @
- 2012 -2015 Design Engineer @
- 2008 -2008 Student Assistant @
- 2007 -2007 Intern @ Twin Antenna
Niravkumar Patel Education
- San Jose State University
Master of Science (MS), Electrical Engineer (Electrical Engineer)
2008-2010 - Hemchandracharya North Gujarat University
Bachelor of Engineering - BE, Electronics & Communication (Electronics & Communication)
2003-2007
Niravkumar Patel Skills
- SystemVerilog
- Hardware Architecture
- Static Timing Analysis
- Cadence Virtuoso
- RTL coding
- VLSI
- Verilog
- SoC
- Very Large Scale Integration Vlsi
- VHDL
- ModelSim
- C
- C++
- System On A Chip Soc
- Functional Verification
- RTL design
- Very Large Scale Integration
- System on a Chip
Niravkumar Patel Summary
- Niravkumar Patel, based in Chandler, AZ, US, is currently a Design Verification Engineer at AMD. Niravkumar Patel brings experience from previous roles at HCLTech, Intel Corporation and Microchip Technology. Niravkumar Patel holds a 2008 - 2010 Master of Science (MS), Electrical Engineer in Electrical Engineer @ San Jose State University. With a robust skill set that includes SystemVerilog, Hardware Architecture, Static Timing Analysis, Cadence Virtuoso, RTL coding and more. Niravkumar Patel has 3 emails and 2 mobile phone numbers on RocketReach.
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