Navin Chander's Location
San Jose, CA, US
Navin Chander's Work
- Vice President of Engineering, MEMS BG @ TDK InvenSense
- Vice President NPI and ASIC Engineering, Microphone BU @ TDK InvenSense
- Vice President ASIC Engineering, Microphone BU @ TDK InvenSense
- Senior Director IC Design @ TDK InvenSense
- Texas Instruments @ Texas Instruments
Navin Chander's Education
- The University of Texas at Austin
MS (Computer Engineering)
1996 - 1998 - University of Madras
BE (Electrical and Electronics Engineering)
1992 - 1996
Navin Chander's Skills
- Design Engineering Manager
- Static Timing Analysis
- RTL design
- Magma
- Perl scripting
- Primetime and Design Compiler
- SoC Design, Development and Verification
- FPGA
- ASIC
- Verilog
Navin Chander's Summary
Navin Chander, based in San Jose, CA, US, is currently a Vice President of Engineering, MEMS BG at TDK InvenSense, bringing experience from previous roles at TDK InvenSense and Texas Instruments. Navin Chander holds a 1996 - 1998 MS in Computer Engineering @ The University of Texas at Austin. With a robust skill set that includes Design Engineering Manager, Static Timing Analysis, RTL design, Magma, Perl scripting and more, Navin Chander contributes valuable insights to the industry. Navin Chander has 2 emails and 1 mobile phone number on RocketReach.
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