Naveen D Email
Sr. Silicon Design Engineer @ AMD
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Naveen D Location
- Bengaluru, KA, IN
Naveen D Work
- Sr. Silicon Design Engineer @ (August 2021 - Present)
- Trainee @ SVM Micro sysstems. (August 2015 - November 2015)
- Verification of a Digital Video Broadcoasting -Satellite services to Handheld Devices(DVB_SH) IP. @ Advanced Numerical Research and Analysis Group (ANURAG) ,DRDO. (September 2014 - July 2015)
- Hybrid Encoded Booth Multiplier with RSA Technique (RSAT). @ Synopsys Compiler Tool (January 2011 - April 2011)
Naveen D Education
- Indian Institute of Science (IISc)
CCE-PROFICIENCE PROGRAMME (Project Management)
2018-2019 - Chaitanya Bharathi Institute Of Technology
Master’s Degree (Embedded systems and VLSI Design)
2013-2015 - Jawaharlal Nehru Technological University
B.Tech (Elecctronic and communication Engg.)
2007-2011
Naveen D Summary
- Naveen D, based in Bengaluru, KA, IN, is currently a Sr. Silicon Design Engineer at AMD. Naveen D brings experience from previous roles at SVM Micro sysstems., Advanced Numerical Research and Analysis Group (ANURAG) ,DRDO. and Synopsys Compiler Tool. Naveen D holds a 2018 - 2019 CCE-PROFICIENCE PROGRAMME in Project Management @ Indian Institute of Science (IISc). Naveen D has 1 emails on RocketReach.
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