Nathan Mai Email & Phone Number
RISC-V CPU Design Verification Engineer @ Andes Technology Corporation
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Nathan Mai Location
- Portland, OR, US
Nathan Mai Work
- RISC-V CPU Design Verification Engineer @ (November 2025 - Present)
- Design Verification Engineer @ (April 2025 - October 2025)
- CPU Verification Engineer @ (February 2019 - January 2025)
- Design Verification Engineer @ (February 2017 - February 2019)
- Senior Design Verification Engineer @ (August 2016 - February 2017)
- Component Design and ASIC Engineer @ (August 2011 - August 2016)
- Design Intern @ Parimics (April 2011 - July 2011)
Nathan Mai Education
- San José State University
Master of Sciences (Electrical Engineering: Digital/ASIC Design)
2009-2011 - University of California, Riverside
Bachelor Degree (Electrical Engineering)
Nathan Mai Skills
- ASIC
- Analog
- Integrated Circuit Design
- RTL design
- SoC
- SystemVerilog
- VLSI
- Verilog
Nathan Mai Summary
- Nathan Mai, based in Portland, OR, US, is currently a RISC-V CPU Design Verification Engineer at Andes Technology. Nathan Mai brings experience from previous roles at Paradigm Works, Inc., Ampere, Intel Corporation and Qualcomm. Nathan Mai holds a 2009 - 2011 Master of Sciences in Electrical Engineering: Digital/ASIC Design @ San José State University. With a robust skill set that includes ASIC, Analog, Integrated Circuit Design, RTL design, SoC and more. Nathan Mai has 3 emails and 1 mobile phone numbers on RocketReach.
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