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Nathan Mai Location
Portland, OR, US
Nathan Mai Work
2025 -now RISC-V CPU Design Verification Engineer @
2025 -2025 Design Verification Engineer @
2019 -2025 CPU Verification Engineer @
2017 -2019 Design Verification Engineer @
2016 -2017 Senior Design Verification Engineer @
2011 -2016 Component Design and ASIC Engineer @
2011 -2011 Design Intern @ Parimics
Nathan Mai Education
San José State University
Master of Sciences (Electrical Engineering: Digital/ASIC Design)
2009-2011
University of California, Riverside
Nathan Mai Skills
Verilog
SystemVerilog
Analog
VLSI
RTL design
ASIC
Integrated Circuit Design
SoC
Nathan Mai Summary
Nathan Mai, based in Portland, OR, US, is currently a RISC-V CPU Design Verification Engineer at Andes Technology. Nathan Mai brings experience from previous roles at Paradigm Works, Inc., Ampere, Intel Corporation and Qualcomm. Nathan Mai holds a 2009 - 2011 Master of Sciences in Electrical Engineering: Digital/ASIC Design @ San José State University. With a robust skill set that includes Verilog, SystemVerilog, Analog, VLSI, RTL design and more. Nathan Mai has 3 emails and 1 mobile phone numbers on RocketReach.
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