Nagarjuna V Location
India
Nagarjuna V Work
- 2026 - now PMTS, Silicon Design Engineer @ AMD
- 2022 - 2026 Sr. Manager, SERDES Analog-Digital Interface Timing Closure Engineer @ Synopsys Inc
- 2021 - 2022 Manager II, SERDES Analog-Digital Interface Timing Closure Engineer @ Synopsys Inc
- 2019 - 2021 A and MS Circuit Design Engineer, Sr II @ Synopsys Inc
- 2017 - 2019 Sr Application Engineer II @ Synopsys Inc
- 2014 - 2017 Sr. Application Engineer I @ Synopsys Inc
- 2011 - 2014 Application Engineer II @ Synopsys Inc
Nagarjuna V Education
- Vellore Institute of Technology
Master of Technology (M.Tech.) (VLSI)
2009 - 2011 - Jawaharlal Nehru Technological University
B.Tech (Electronics and Communication Engineering)
2005 - 2009
Nagarjuna V Skills
- Verilog
- Static Timing Analysis
- Integrated Circuit Design
- Low-power Design
- CMOS
- VLSI
- ASIC
- SystemVerilog
- EDA
- VHDL
Nagarjuna V Summary
Nagarjuna V, based in India, is currently a PMTS, Silicon Design Engineer at AMD. Nagarjuna V brings experience from previous roles at Synopsys Inc. Nagarjuna V holds a 2009 - 2011 Master of Technology (M.Tech.) in VLSI @ Vellore Institute of Technology. With a robust skill set that includes Verilog, Static Timing Analysis, Integrated Circuit Design, Low-power Design, CMOS and more. Nagarjuna V has 3 emails on RocketReach.
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