Mujahid Mohammed Email & Phone Number

Mujahid Mohammed Skills

• Full Chip TIMING CLOSURE FOR INTEL XEON SERVER CHIPS using PT-DMSA ECO TOOLS
• Full Chip TIMING CLOSURE FOR INTEL XEON SERVER CHIPS using TWEAKER ECO TOOLS
• Full Chip TIMING CLOSURE FOR INTEL XEON SERVER CHIPS using PRIME CLOSURE ECO TOOLS
• Full Chip INPUT OUTPUT BUDGETING FLOWS FOR INTEL XEON SERVER CHIPS
• Full Chip constraints development for INTEL XEON SERVER CHIPS
• HSPICE SIMULATIONS TO ESTIMATE AGING GUARDBANDS
• Dynamic Voltage Drop (DVD) AWARE CLOCK JITTER FLOWS
• timing constraint generation for partitions/blocks
• Physical Design
• Static Timing Analysis
• Primetime
• VLSI
• Physical Verification
• Floorplanning
• ICC
• SoC
• LVS
• TCL
• Clock Tree Synthesis
• Timing Closure
• Formal Verification
• SystemVerilog
• ASIC
• Magma
• Synopsys tools
• CMOS
• VHDL
• Analog Circuit Design
• Analog
• Digital Electronics
• IC
• Semiconductors
• Logic Design
• EDA
• Mixed Signal
• Microprocessors
• Verilog
• Debugging
• RC Extraction
• Perl
• Cadence
• SPICE
• Open Verification Methodology
• Processors
• Integrated Circuit Design
• Cadence Encounter
• ARM
• Logic Synthesis
• Cadence Virtuoso
• Signal Integrity
• Low-power Design
• Power Analysis
• IC COMPILER
• CADENCE SOC ENCOUNTER
• 14nm DRC fixing
• 14nm patternmatch fixing
• familiar with all aspects of ASIC integration including Floorplanning, Clock and
• Clock
• Design
• DRC
• Low Power Design
• Familiar With All Aspects Of Asic Integration Including Floorplanning