Software (RTL) Enabling and Optimization Engineer @ (May 2023 - December 2024)
FPGA IP Software (RTL) Development Engineer (Senior MTS) @ (November 2021 - April 2023)
IP Logic Design Engineer (Senior MTS) @ (November 2016 - October 2021)
Member Of Technical Staff Design Engineer @ (January 2016 - October 2016)
Technical Lead @ (December 2013 - January 2016)
Principal Design Engineer @ Silicon Design Solutions (SDS) (March 2013 - December 2013)
Principal Design Engineer @ (April 2012 - February 2013)
Principal Design Engineer @ (October 2011 - March 2012)
Senior Design Engineer @ (July 2010 - September 2011)
Design Engineer @ (October 2007 - June 2010)
Muhammad Hafeez Education
COMSATS Institute of Information and Technology
BS/BE (Computer Engineering)
2003-2007
Muhammad Hafeez Skills
Hybrid Competence
Verilog
FPGA
ASIC
Embedded Systems
SystemVerilog
SoC
C
Microcontrollers
Integrated Circuit Design
Firmware
RTL design
UVM
Xilinx
Embedded C
USB
I2C
ARM
C++
Keil
ModelSim
Debugging
Computer Architecture
Digital Signal Processors
Assembly
SPI
Hardware Architecture
Python
Shell Scripting
Perl
Testing
Matlab
SystemC
Socket Programming
Altera Quartus
VCS
Programming
Hardware
Emulator
Questa
Veloce
Field-Programmable Gate Arrays (FPGA)
Planning
Field Programmable Gate Arrays Fpga
Graphics
Scheduling
Design
Field Programmable Gate Arrays
Muhammad Hafeez Summary
Muhammad Hafeez, based in San Jose, CA, US, is currently a Software (RTL) Enabling and Optimization Engineer at Altera. Muhammad Hafeez brings experience from previous roles at Intel Corporation. Muhammad Hafeez holds a 2003 - 2007 BS/BE in Computer Engineering @ COMSATS Institute of Information and Technology. With a robust skill set that includes Hybrid Competence, Verilog, FPGA, ASIC, Embedded Systems and more. Muhammad Hafeez has 2 emails and 1 mobile phone numbers on RocketReach.
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