Mridul Verma Email
Senior Lead Engineer (GPU STA) @ Qualcomm
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Mridul Verma Location
- Noida, UP, IN
Mridul Verma Work
- Senior Lead Engineer (GPU STA) @ (September 2025 - Present)
- LEAD DIGITAL PHYSICAL DESIGN ENGINEER @ (April 2024 - September 2025)
- Digital Physical Design Engineer @ (May 2022 - March 2024)
- Application Engineer II @ (July 2020 - April 2022)
- AMS Layout Design Engineer II @ (June 2020 - July 2020)
- A and MS Layout Design Engr, I @ (March 2018 - June 2020)
- Standard cell layout design Intern @ (August 2017 - March 2018)
- Trainee @ (September 2016 - July 2017)
- Intern @ Tech Adityaa (June 2016 - July 2016)
- Project Trainee @ CFEES Laboratory, D.R.D.O. (June 2016 - July 2016)
Mridul Verma Education
- ABES Engineering College
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2013-2017 - Brij Bhushan Lal public school, Bareilly
Higher secondary examination (PCM+Computer science)
1999-2013
Mridul Verma Skills
- Analog Layout Design
- Bash
- Bash Scripting
- C
- C++
- Cadence Encounter
- Cadence Schematic Capture
- Cadence Spectre
- Cadence Virtuoso
- Cadence Virtuoso Layout Editor
- Custom designer
- Design Rule Checking (DRC)
- Digital Circuit Design
- Field-Programmable Gate Arrays (FPGA)
- Finfet
- Layout Versus Schematic (LVS)
- Linux
- Microsoft Word
- Perl
- Perl Scripting
- RC Extraction
- SMIC 14nm node
- Samsung 8nm node
- Standard cell layout design
- Static Timing Analysis
- Synopsys Primetime
- TCL
- TCL Scripting
- TSMC 12nm node
- TSMC 16nm node
- TSMC N5 node
- TSMC N7+ node
- TSMC N7nm node
- Timing Closure
- Ubuntu
- Unix Commands
- Verilog
- Very-Large-Scale Integration (VLSI)
- Windows
- Xilinx ISE
- timing constraints
- PowerPoint
- Digital Electronics
- Field Programmable Gate Arrays Fpga
- Layout Versus Schematic Lvs
- Matlab
- Electronics
- Design Rule Checking Drc
- Microsoft Office
- Java
- Embedded Systems
- Microsoft Excel
- Management
- Very Large Scale Integration Vlsi
- Very Large Scale Integration
- Field Programmable Gate Arrays
- Design Rule Checking
- Layout Versus Schematic
Mridul Verma Summary
- Mridul Verma, based in Noida, UP, IN, is currently a Senior Lead Engineer (GPU STA) at Qualcomm. Mridul Verma brings experience from previous roles at NXP Semiconductors and Synopsys Inc. Mridul Verma holds a 2013 - 2017 Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering @ ABES Engineering College. With a robust skill set that includes Analog Layout Design, Bash, Bash Scripting, C, C++ and more. Mridul Verma has 3 emails on RocketReach.
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