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Ming Lin Location
San Jose, CA, US
Ming Lin Work
Principal Engineer @ (November 2016 - Present)
RFIC Digital Design Engineer @ (December 2013 - November 2016)
Sr. Staff Design Engineer @ (July 2006 - December 2013)
ASIC Design Engineer @ (November 2004 - July 2006)
Ming Lin Education
UCLA
MS (Electrical Engineering (IC&S))
2002-2004
National Tsing Hua University
Bachelor of Science (Electrical Engineering)
1996-2000
Ming Lin Skills
ASIC
Application-Specific Integrated Circuits (ASIC)
CMOS
Cross-functional Coordination
DFT
Debugging
Design Specifications
Digital IC Design
Digital Signal Processing
FPGA
Field-Programmable Gate Arrays (FPGA)
High-speed Digital Design
IC
Integrated Circuit Design
Integrated Circuits (IC)
PLL
Project Planning
RF
RTL design
Schedule Planning
SoC
Synthesis
SystemVerilog
Team Building
Team Leadership
Team Management
VLSI
Verilog
Very-Large-Scale Integration (VLSI)
WiFi
Ming Lin Summary
Ming Lin, based in San Jose, CA, US, is currently a Principal Engineer at Qualcomm. Ming Lin brings experience from previous roles at Apple, Marvell Semiconductor and Axiom Microdevices. Ming Lin holds a 2002 - 2004 MS in Electrical Engineering (IC&S) @ UCLA. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), CMOS, Cross-functional Coordination, DFT and more. Ming Lin has 3 emails and 2 mobile phone numbers on RocketReach.
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