Mike Foreman Email & Phone Number
GDDR Physical Design Lead @ Intel Corporation
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Mike Foreman Location
- Livermore, CA, US
Mike Foreman Work
- GDDR Physical Design Lead @ (July 2007 - Present)
- Senior Digital Mask Designer @ (September 2002 - October 2006)
- Mask Designer @ (January 1997 - September 2002)
- Sergeant @ (May 1992 - May 1996)
Mike Foreman Education
- University Of California - Santa Cruz
(Engineering)
2013-2014 - California State University - East Bay
Bachelor Of Science (Geography)
1989-1991
Mike Foreman Skills
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- Arduino
- CMOS
- Cadence Virtuoso
- Clock Distribution
- DRC
- Debugging
- EDA
- Floorplanning
- Hercules
- IC
- IC layout
- LVS
- Mixed Signal
- PLL
- Physical Design
- Physical Verification
- Semiconductors
- SoC
- Static Timing Analysis
- System on a Chip (SoC)
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- Virtuoso
Mike Foreman Summary
- Mike Foreman, based in Livermore, CA, US, is currently a GDDR Physical Design Lead at Intel Corporation. Mike Foreman brings experience from previous roles at Intel Corporation and Us Army. Mike Foreman holds a 2013 - 2014 University Of California - Santa Cruz. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), Arduino, CMOS, Cadence Virtuoso and more. Mike Foreman has 1 emails and 1 mobile phone numbers on RocketReach.
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