Michael Vasicek Email
Lead Chip Design Engineer @ Numascale AS
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Michael Vasicek Location
- Prague, Czechia
Michael Vasicek Work
- Lead Chip Design Engineer @ (January 2009 - Present)
- Lead Chip Design Engineer @ (May 2007 - December 2008)
- Principal Design Engineer @ Stargen (January 1999 - January 2007)
- Senior Design Engineer @ (July 1998 - August 1999)
- Chip Design Engineer @ (August 1993 - July 1998)
Michael Vasicek Education
- University of Finance and Administration, Prague
Master's degree (Informatics)
2009-2011 - Tufts University
BSEE (Electrical Engineering)
1989-1993
Michael Vasicek Skills
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- C++
- Cache Coherency
- Chip Architecture
- Debugging
- FPGA
- Field-Programmable Gate Arrays (FPGA)
- Hardware
- HyperTransport
- IC
- Integrated Circuit Design
- Logic Design
- Logic Synthesis
- PCIe
- Perl
- RTL design
- RTL verification
- SCI
- Simulation
- Software Engineering
- Synopsys tools
- SystemVerilog
- Testing
- UPI
- UVM
- UltraPath Interconnect
- Verilog
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Michael Vasicek Summary
- Michael Vasicek, based in Prague, Czechia, is currently a Lead Chip Design Engineer at NumaScale. Michael Vasicek brings experience from previous roles at Dolphin Interconnect Solutions, Stargen, Intel and Digital Equipment Corporation. Michael Vasicek holds a 2009 - 2011 Master's degree in Informatics @ University of Finance and Administration, Prague. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), C++, Cache Coherency, Chip Architecture and more. Michael Vasicek has 2 emails on RocketReach.
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