ASIC and FPGA Design Engineer @ (April 2000 - November 2004)
Sr. ASIC and Physical Designer @ (February 1998 - April 2000)
ASIC Design Engineer @ (April 1996 - February 1998)
Hardware Engineer @ (June 1992 - April 1996)
Design Verification Engineer @ (June 1990 - May 1994)
Michael Ruff Education
Purdue University
BSCEE (Electrical, Computer)
1986-1990
Michael Ruff Skills
ASIC
FPGA
Verilog
Xilinx
SystemC
Embedded Systems
Perl
Unix
Linux
C
RTL design
Static Timing Analysis
Timing Closure
RTL coding
High Performance Computing
TCL
Primetime
VCS
Altera
C++
VHDL
NC-Verilog
Computer Hardware
System Administration
NetApp
Reconfigurable Computing
Application Servers
BLAST
BWA
Dynamic Programming
Floorplanning
Asynchronous
Cache Coherency
Memory Management
High Speed Digital
Virtex
SPICE
Design Verification Testing
Computer Architecture
Functional Verification
Hardware Architecture
SystemVerilog
Physical Design
Microprocessors
Simulations
CMOS
Compilers
Application-Specific Integrated Circuits (ASIC)
Field-Programmable Gate Arrays (FPGA)
Nc Verilog
Michael Ruff Summary
Michael Ruff, based in Richardson, TX, US, is currently a Principal Engineer, Member of CTO Staff at SiFive. Michael Ruff brings experience from previous roles at Microsoft, Intel Corporation and Micron Technology. Michael Ruff holds a 1986 - 1990 BSCEE in Electrical, Computer @ Purdue University. With a robust skill set that includes ASIC, FPGA, Verilog, Xilinx, SystemC and more. Michael Ruff has 3 emails and 4 mobile phone numbers on RocketReach.
Looking for a different Michael Ruff?
Find contact details for 700 million professionals.