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Michael Ruff Location
Richardson, TX, US
Michael Ruff Work
2022 -now Principal Engineer, Member of CTO Staff @
2019 -2022 Principal Hardware Engineer @
2017 -2019 Senior Hardware Design Engineer @
2015 -2017 Staff Design Engineer @
2015 -2015 Hardware Development Engineer @
2007 -2015 Design Engineer @
2005 -2007 Sr. ASIC Designer - Wireless @
2000 -2004 ASIC and FPGA Design Engineer @
1998 -2000 Sr. ASIC and Physical Designer @
1996 -1998 ASIC Design Engineer @
1992 -1996 Hardware Engineer @
1990 -1994 Design Verification Engineer @
Michael Ruff Education
Purdue University
BSCEE (Electrical, Computer)
1986-1990
Michael Ruff Skills
ASIC
FPGA
Verilog
Xilinx
SystemC
Embedded Systems
Perl
Unix
Linux
C
RTL design
Static Timing Analysis
Timing Closure
RTL coding
High Performance Computing
TCL
Primetime
VCS
Altera
C++
VHDL
NC-Verilog
Computer Hardware
System Administration
NetApp
Reconfigurable Computing
Application Servers
BLAST
BWA
Dynamic Programming
Floorplanning
Asynchronous
Cache Coherency
Memory Management
High Speed Digital
Virtex
SPICE
Design Verification Testing
Computer Architecture
Functional Verification
Hardware Architecture
SystemVerilog
Physical Design
Microprocessors
Simulations
CMOS
Compilers
Application-Specific Integrated Circuits (ASIC)
Field-Programmable Gate Arrays (FPGA)
Nc Verilog
Michael Ruff Summary
Michael Ruff, based in Richardson, TX, US, is currently a Principal Engineer, Member of CTO Staff at SiFive. Michael Ruff brings experience from previous roles at Microsoft, Intel Corporation and Micron Technology. Michael Ruff holds a 1986 - 1990 BSCEE in Electrical, Computer @ Purdue University. With a robust skill set that includes ASIC, FPGA, Verilog, Xilinx, SystemC and more. Michael Ruff has 3 emails and 4 mobile phone numbers on RocketReach.
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