Senior Design Engineer - II (Emulation) @ (November 2022 - January 2026)
Senior Design Engineer - I (Emulation) @ (May 2021 - December 2022)
Design Engineer - II @ (May 2020 - May 2021)
ASIC Design Engineering Intern @ Scalable Systems Research Labs Inc. (July 2016 - March 2017)
Design Engineer - II @ (June 2019 - May 2020)
Design Engineer - I @ (March 2017 - June 2019)
Graduate Student @ (August 2014 - May 2016)
President @ Electronics and Telecommunication Students Association (February 2013 - May 2014)
Merin Thomas Education
The University of Texas at Dallas
Master of Science (MS) (Electrical and Electronics Engineering)
2014-2016
Savitribai Phule Pune University
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
2010-2014
Merin Thomas Skills
PowerPoint
Cadence Virtuoso
Layout Design
Linux
Illustrator
Human Resources
C
Windows
Graphic Design
SPICE
Perl
Logic Synthesis
Functional Verification
Matlab
Photoshop
Teaching
RTL design
ASIC
Xilinx ISE
VLSI
Verilog
Microcontrollers
Place And Route
Cadence Encounter
HTML
Microsoft Office
Programming
Microsoft Word
Java
Microsoft Excel
FPGA
SoC
Electrical Engineering
VHDL
C++
Synopsys Primetime
Python
SystemVerilog
Synopsys tools
Cadence Spectre
Physical Design
Teamwork
Research
Static Timing Analysis
Unix
Very Large Scale Integration Vlsi
Digital Circuit Design
Very Large Scale Integration
Merin Thomas Summary
Merin Thomas, based in Sacramento, CA, US, is currently a Staff Emulation Engineer at Qualcomm. Merin Thomas brings experience from previous roles at Microchip Technology Inc. and Scalable Systems Research Labs Inc.. Merin Thomas holds a 2014 - 2016 Master of Science (MS) in Electrical and Electronics Engineering @ The University of Texas at Dallas. With a robust skill set that includes PowerPoint, Cadence Virtuoso, Layout Design, Linux, Illustrator and more. Merin Thomas has 3 emails and 3 mobile phone numbers on RocketReach.
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