Melody Chiu Email & Phone Number
IP Logic Design Engineer @ Intel Corporation
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Melody Chiu Location
- San Jose, CA, US
Melody Chiu Work
- IP Logic Design Engineer @ (January 2023 - Present)
- SoC Design Engineer @ (January 2017 - January 2023)
- SoC Design Engineer @ (January 2015 - January 2017)
- Component Design Engineer @ (January 2011 - January 2015)
- Component Design Engineer @ (January 2005 - January 2011)
Melody Chiu Education
- University of Southern California
Masters (Electrical Engineering)
2003-2004 - National Tsing Hua University
BS (Electrical Engineering)
1999-2003
Melody Chiu Skills
- RTL Design
- RTL-FEV Alignment
- SoC & IP Integration
- SystemVerilog
- Unified Power Format (UPF)
- Component Design
- ModelSim
Melody Chiu Summary
- Melody Chiu, based in San Jose, CA, US, is currently a IP Logic Design Engineer at Intel Corporation. Melody Chiu brings experience from previous roles at Intel Corporation. Melody Chiu holds a 2003 - 2004 Masters in Electrical Engineering @ University of Southern California. With a robust skill set that includes RTL Design, RTL-FEV Alignment, SoC & IP Integration, SystemVerilog, Unified Power Format (UPF) and more. Melody Chiu has 2 emails and 1 mobile phone numbers on RocketReach.
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