Max Bjurling Location
- Ödeshög, SE
Max Bjurling Work
- 2024 -now Digital Design Engineer @
- 2015 -now ASIC and FPGA Designer @
- 2023 -2024 Digital Design Engineer @
- 2018 -2023 Digital ASIC Designer @
- 2016 -2017 FPGA Designer @
- 2016 -2017 FPGA Designer @
- 2012 -2015 Senior ASIC Design Engineer @
- 2009 -2012 Digital ASIC Designer @
- 2006 -2008 FPGA Designer @
- 2004 -2006 IC Designer @
Max Bjurling Education
- The Faculty of Engineering at Lund University 1997-2003
- Luleå University of Technology 1995-1997
Max Bjurling Skills
- Hardware Architecture
- Logic Design
- Field Programmable Gate Arrays Fpga
- Embroidery
- C
- Debugging
- Logic Synthesis
- Functional Verification
- RTL design
- ASIC
- Digital Design
- Electronics
- VLSI
- Verilog
- Integrated Circuit Design
- Formal Verification
- Cadence
- TCL
- Mixed Signal
- Embedded Systems
- Application Specific Integrated Circuits Asic
- FPGA
- RTL coding
- SoC
- VHDL
- EDA
- ModelSim
- Timing Closure
- SystemVerilog
- Semiconductors
- Physical Design
- Static Timing Analysis
- Digital Signal Processors
- Low Power Design
- Wedding Planning
- IC
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Max Bjurling Summary
- Max Bjurling, based in Ödeshög, SE, is currently a Digital Design Engineer at ExpectedIT. Max Bjurling brings experience from previous roles at Bjurling Logic, PlanV, yDesign AB and Sigma Technology AB. Max Bjurling holds a 1997 - 2003 The Faculty of Engineering at Lund University. With a robust skill set that includes Hardware Architecture, Logic Design, Field Programmable Gate Arrays Fpga, Embroidery, C and more. Max Bjurling has 3 emails on RocketReach.
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