Mathieu Maisonneuve Email
Verification Engineer ASIC FPGA @ Thales
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Mathieu Maisonneuve Location
- Bengaluru, KA, IN
Mathieu Maisonneuve Work
- 2023 -now Verification Engineer ASIC FPGA @
- 2016 -2023 Verification Engineer ASIC FPGA @
- 2015 -2016 Verification Engineer @ MAYA TECHNOLOGIES
- 2012 -2015 Verification Engineer @
Mathieu Maisonneuve Education
- Grenoble INP - Phelma
Engineer's degree (Integrated Electronic Systems)
2009-2012
Mathieu Maisonneuve Skills
- Functional Verification
- SystemVerilog
- UVM
- SystemC
- SoC
- Assembly
- Verilog
- VHDL
- RTL design
- ASIC
- VLSI
- TCL
- Perl
- Vérification fonctionnelle
- C
- C++
- Microsoft Office
- Microsoft Excel
- Sap Bfc
- Microsoft Word
- PowerPoint
- Audit financier
Mathieu Maisonneuve Summary
- Mathieu Maisonneuve, based in Bengaluru, KA, IN, is currently a Verification Engineer ASIC FPGA at Thales. Mathieu Maisonneuve brings experience from previous roles at Thales, MAYA TECHNOLOGIES and Test and Verification Solutions. Mathieu Maisonneuve holds a 2009 - 2012 Engineer's degree in Integrated Electronic Systems @ Grenoble INP - Phelma. With a robust skill set that includes Functional Verification, SystemVerilog, UVM, SystemC, SoC and more. Mathieu Maisonneuve has 2 emails on RocketReach.
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