Mathieu Maisonneuve Email
FPGA Hardware Engineering Manager @ Thales
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Mathieu Maisonneuve Location
- Paris, FR
Mathieu Maisonneuve Work
- FPGA Hardware Engineering Manager @ (October 2025 - Present)
- Verification Engineer ASIC FPGA @ (October 2023 - April 2026)
- Verification Engineer ASIC FPGA @ (November 2016 - September 2023)
- Verification Engineer @ MAYA TECHNOLOGIES (January 2015 - October 2016)
- Verification Engineer @ (August 2012 - January 2015)
Mathieu Maisonneuve Education
- Grenoble INP - Phelma
Engineer's degree (Integrated Electronic Systems)
2009-2012
Mathieu Maisonneuve Skills
- Functional Verification
- SystemVerilog
- UVM
- SystemC
- SoC
- Assembly
- Verilog
- VHDL
- RTL design
- ASIC
- VLSI
- TCL
- Perl
- Vérification fonctionnelle
- C
- C++
- Microsoft Office
- Microsoft Excel
- Sap Bfc
- Microsoft Word
- PowerPoint
- Audit financier
Mathieu Maisonneuve Summary
- Mathieu Maisonneuve, based in Paris, FR, is currently a FPGA Hardware Engineering Manager at Thales. Mathieu Maisonneuve brings experience from previous roles at Thales, MAYA TECHNOLOGIES and Test and Verification Solutions. Mathieu Maisonneuve holds a 2009 - 2012 Engineer's degree in Integrated Electronic Systems @ Grenoble INP - Phelma. With a robust skill set that includes Functional Verification, SystemVerilog, UVM, SystemC, SoC and more. Mathieu Maisonneuve has 2 emails on RocketReach.
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