Matej MacHalec Email

Matej MacHalec Skills

• ASIC
• FPGA
• RTL design
• Logic synthesis
• Static Timing Analysis
• DFT
• ATPG
• Integrated circuits
• Simulation
• VHDL
• Verilog
• LEC
• UPF
• timing constraints
• SDC
• Digital design
• Low-power design
• design team leading
• SCAN
• Perl
• SoC
• Synopsys Design Compiler
• Synopsys DFT Compiler
• Synopsys PrimeTime
• Synopsys PrimeTime PX
• Synopsys TetraMax
• Synopsys Formality
• Cadence Innovus Implementation System
• Cadence Encounter
• Cadence NCSim
• Cadence CCD (CDC)
• Power analysis
• Cadence Ccd Cdc
• Low Power Design
• Cadence CCD