Mary Low Email & Phone Number
Director Design Project and Program Manager - ASIC Design @ Rivian
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Mary Low Location
- San Jose, CA, US
Mary Low Work
- 2023 -now Director Design Project and Program Manager - ASIC Design @
- 2023 -now Director Design Project and Program Manager - Special Projects @
- 2022 -2023 Program Manager - ASIC Design @
- 2022 -2023 Program Manager - Special Projects @
- 2019 -2022 Director, Silicon Systems Application and Validation Team @
- 2017 -2019 Director @
- 2013 -2017 Senior Design Manager @
- 2010 -2013 Senior SerDes Applications Manager @
- 2010 -2010 Protocol Applications Manager - SERDES Technology Group @
- 2006 -2010 Staff Design Engineer - RocketIO Applications @
- 2002 -2006 Senior Design Engineer - Systems Engineering Group @
- 2001 -2002 Design Engineer - XCoNET @
Mary Low Education
- University of Pennsylvania
BS & MS (Electrical Engineering)
1998-2001 - New Jersey Institute of Technology
BS (Electrical Engineering)
1997-1998
Mary Low Skills
- Verilog
- Xilinx ISE
- PCIe
- VHDL
- Ethernet
- Logic Design
- RTL design
- Semiconductor Industry
- FPGA
- EDA
- Systems Engineering
- Field Programmable Gate Arrays Fpga
- Research
- Semiconductors
- Applications
- Design
- SERDES
- Integration
- Business Analysis
- Field Programmable Gate Arrays
Mary Low Summary
- Mary Low, based in San Jose, CA, US, is currently a Director Design Project and Program Manager - ASIC Design at Rivian. Mary Low brings experience from previous roles at Rivian and Xilinx. Mary Low holds a 1998 - 2001 BS & MS in Electrical Engineering @ University of Pennsylvania. With a robust skill set that includes Verilog, Xilinx ISE, PCIe, VHDL, Ethernet and more. Mary Low has 1 mobile phone numbers on RocketReach.
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