Marko Olujić Email
Design Verification Engineer @ Verilab
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Marko Olujić Location
- Berlin, DE
Marko Olujić Work
- 2016 -now Design Verification Engineer @
- 2009 -2016 Senior Verification Engineer @
Marko Olujić Education
- Faculty of Technical Sciences in Novi Sad
Master of Science (Electrical and Computer Engineering)
2001-2007
Marko Olujić Skills
- Specman
- NCSim
- VMM
- Functional Verification
- SystemVerilog
- RTL design
- Verilog
- ModelSim
- SoC
- FPGA
- RTL coding
- Open Verification Methodology
- Debugging
- ASIC
- Integrated Circuit Design
- AMBA AHB
- UVM
- RTL verification
- PCIe
- VHDL
- VLSI
- C
- Embedded Systems
- Linux
- C++
- IC
- Simulations
- EDA
- Semiconductors
- Microcontrollers
- Cadence Virtuoso
- Formal Verification
Marko Olujić Summary
- Marko Olujić, based in Berlin, DE, is currently a Design Verification Engineer at Verilab. Marko Olujić brings experience from previous roles at HDL Design House. Marko Olujić holds a 2001 - 2007 Master of Science in Electrical and Computer Engineering @ Faculty of Technical Sciences in Novi Sad. With a robust skill set that includes Specman, NCSim, VMM, Functional Verification, SystemVerilog and more. Marko Olujić has 2 emails on RocketReach.
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