PSF Automation Verification @ (January 2016 - January 2017)
eSPI micro-architect @ (January 2014 - January 2015)
Innovation Engine (IE) micro-architect @ (January 2013 - January 2014)
IE UART @ (January 2013 - January 2014)
Security Engine Verification @ (January 2011 - January 2014)
HSI ownership @ (January 2010 - January 2011)
UMG SOC Performance Team @ (January 2009 - January 2011)
Owner of the NAND Cluster @ (January 2008 - January 2009)
Media Performance Simulator @ (January 2006 - January 2008)
3D Performance Verification @ (January 2005 - January 2006)
Owner of multiple 3D and 2D units @ (January 2000 - January 2006)
GLS, and COSIM, and PV Partition Owner @ (January 2000 - January 2002)
Chipset Unit Owner @ (January 1998 - January 2001)
Chipset Validation @ (January 1996 - January 1998)
Mark Sabol Education
University of Washington
Bachelor’s Degree (Electrical and Electronics Engineering)
Mark Sabol Skills
SystemVerilog
Semiconductors
Embedded Systems
ASIC
Synopsys Synthesis
Computer Architecture
SoC
Verilog
VLSI
Synopsys Dve
VHDL
Engineering
C++
C
Debugging
Hardware
System Verilog
Perl
RTL design
Mark Sabol Summary
Mark Sabol, based in San Diego, CA, US, is currently a Senior Design Verification Engineer at Qualcomm. Mark Sabol brings experience from previous roles at Intel Corporation. Mark Sabol holds a Bachelor’s Degree in Electrical and Electronics Engineering @ University of Washington. With a robust skill set that includes SystemVerilog, Semiconductors, Embedded Systems, ASIC, Synopsys Synthesis and more. Mark Sabol has 5 emails and 2 mobile phone numbers on RocketReach.
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