Mark Rempel Email & Phone Number
PMTS Silicon Design Engineer @ AMD
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Mark Rempel Location
- Burlingame, CA, US
Mark Rempel Work
- 2023 -now PMTS Silicon Design Engineer @
- 2019 -2023 Principal Design Engineer @
- 2018 -2019 Principal Hardware Engineer @
- 2017 -2018 MTS @ Innovium Inc.
- 2010 -2017 Principal Hardware Engineer @
- 2004 -2010 Senior Hardware Engineer @
- 1996 -2004 Sr Component Design Engineer @
Mark Rempel Education
- University of Pittsburgh
MSEE (Electrical Engineering)
1993-1996 - University of Pittsburgh
BSEE (Electrical Engineering)
1989-1993
Mark Rempel Skills
- Development
- Cadence Skill
- Cadence Virtuoso
- C
- Computer Hardware
- Debugging
- Physical Verification
- Perl
- Data Validation
- Processors
- CAD
- Team Leadership
- Validation
- TCL
- Tcl Tk
- Application Specific Integrated Circuits Asic
- Synopsis Icc
- C++
- Python
- Synopsys tools
- Physical Design
- Computer Aided Design Cad
- Very Large Scale Integration Vlsi
- Integration
- IC
- Application Specific Integrated Circuits
- Very Large Scale Integration
- Computer Aided Design
- Semiconductors
- System on a Chip
- Timing Closure
Mark Rempel Summary
- Mark Rempel, based in Burlingame, CA, US, is currently a PMTS Silicon Design Engineer at AMD. Mark Rempel brings experience from previous roles at quadric.io, Arteris IP, Innovium Inc. and Oracle. Mark Rempel holds a 1993 - 1996 MSEE in Electrical Engineering @ University of Pittsburgh. With a robust skill set that includes Development, Cadence Skill, Cadence Virtuoso, C, Computer Hardware and more. Mark Rempel has 2 emails and 6 mobile phone numbers on RocketReach.
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