Engineering Manager @ (February 2024 - August 2026)
Principal Process Integration Engineer @ (October 2018 - December 2023)
Sr Manager of Process Engineering @ (October 2018 - December 2023)
Design Rule Validation Engineer @ (January 2015 - January 2018)
Technology Development FEOL Integration Engineer @ (January 2010 - January 2015)
FEOL Integration Engineer @ (January 2010 - January 2010)
Plasma Etch Engineer @ (January 2005 - January 2010)
Thin Films Development Engineer @ (January 2000 - May 2005)
Etch Process Owner @ White Oak Semiconductor (January 1997 - January 2000)
Mark Curtice Education
Columbia Engineering
MS (Materials Science)
University of Southern Maine
BS (Electrical Engineering)
Mark Curtice Skills
CMOS
CVD
Characterization
Design Enablement
Design of Experiments
Engineering Management
Etching
GaN
IC
Integration
JMP
Management
Metrology
Plasma Etch
Process Integration
Product Development
Semiconductor Engineering
Semiconductor Industry
Semiconductor Process
Semiconductors
Silicon
Sputtering
Thin Films
Yield
Mark Curtice Summary
Mark Curtice, based in Coventry, RI, US, is currently a Etch Engineering Manager at Wolfspeed. Mark Curtice brings experience from previous roles at Vishay Electro-Films,Inc., NEXGEN POWER SYSTEMS and GLOBALFOUNDRIES. Mark Curtice holds a MS in Materials Science @ Columbia Engineering. With a robust skill set that includes CMOS, CVD, Characterization, Design Enablement, Design of Experiments and more. Mark Curtice has 2 emails and 3 mobile phone numbers on RocketReach.
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