Marco Desogus Email
Senior FPGA Engineer @ Celestia STS
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Marco Desogus Location
- Leiden, ZH, NL
Marco Desogus Work
- Senior FPGA Engineer @ (April 2020 - Present)
- Technical Lead - FPGA Design and Verification Engineer @ (October 2016 - March 2020)
- Senior Developer - FPGA Design and Verification Engineer @ (February 2015 - October 2016)
- Research Assistant - FPGA Developer for European Space Agency (ESA) @ (January 2013 - January 2015)
- Research Assistant - FPGA Developer for Pirelli Tyre S.p.A. @ (December 2011 - December 2013)
Marco Desogus Education
- Politecnico di Torino
Master of Science (M.Sc.) (Electronic enginnering)
2009-2011 - ESIGELEC : ÉCOLE D'INGÉNIEURS-ES GÉNÉRALISTES
ERASMUS (Embedded System)
2009-2010 - Politecnico di Torino
Bachelor's degree (Electronics Engineering)
2005-2009 - ITIS Othoca
Diploma electrical engineering technician (Electrical, Electronics and Communications Engineering)
2000-2005
Marco Desogus Skills
- VHDL
- FPGA
- Verilog
- Tetramax
- Xilinx
- Altera
- ModelSim
- ASIC
- Synopsys tools
- Cadence
- C
- Assembly Language
- Assembler
- Matlab
- Labview
- AutoCAD
- CodeWarrior
- AWR Microwave Office
- Keil
- Bash
- TCL
- Reconfigurable Computing
- Linux Kernel
- Embedded Linux
- Kernel Drivers
- SystemVerilog
- Microsoft Office
- Git
- ClearCase
- Java
- Engineering
- Microsoft Excel
- Research
Marco Desogus Summary
- Marco Desogus, based in Leiden, ZH, NL, is currently a Senior FPGA Engineer at Celestia Satellite Test & Simulation BV. Marco Desogus brings experience from previous roles at HCL Technologies and Politecnico di Torino. Marco Desogus holds a 2009 - 2011 Master of Science (M.Sc.) in Electronic enginnering @ Politecnico di Torino. With a robust skill set that includes VHDL, FPGA, Verilog, Tetramax, Xilinx and more. Marco Desogus has 1 emails on RocketReach.
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