Marcelo Jara Email
ASIC and SoC Physical Design and Timing Analysis Sr Technical Manag. @ HCL America, Inc.
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Marcelo Jara Location
- State of São Paulo, Brazil
Marcelo Jara Work
- 2022 -now ASIC and SoC Physical Design and Timing Analysis Sr Technical Manag. @
- 2020 -2022 R and D SoC and ASIC Sr Phys Design @
- 2018 -2019 Postdoctoral Researcher @ State University of Campinas
- 2017 -2018 SoC Digital and Physical Design @
- 2015 -2016 SoC and ASIC physical design - Electronics and Communication systems @ Idea! Electronic Systems
- 2012 -2015 R and D and SoC ASIC Design Engineer @
- now R and D SoC and ASIC Design @
- 2000 -2009 Sr Design Engineer @
- 1999 -2000 Systems Engineer @
- 1997 -1999 SoC Researcher @ Magneti Marelli Research Lab at Unicamp
Marcelo Jara Education
- Universidade Estadual de Campinas
PhD on EE, MSc on EE (Electrical Eng (FEE/DSIF), VLSI design, Parallel processing, Artificial Neural Networks)
1990-1996 - Universidade Federal do Rio de Janeiro COPPE
Eng. (Computer Architecture)
- Universidad Austral de Chile
Marcelo Jara Skills
- Application Specific Integrated Circuits Asic
- RTL design
- Logic Synthesis
- VLSI
- Electronics
- Microcontrollers
- Functional Verification
- Digital Signal Processors
- Troubleshooting
- Research and Development R&d
- Physical Design
- Ic Design
- IC
- Engineering
- VHDL
- Digital Design
- Integrated Circuits Ic
- Low Power Design
- RF
- Very Large Scale Integration Vlsi
- Timing Closure
- SoC
- Social Media Marketing
- Embedded Systems
- Computer Architecture
- Data Analysis
- Design
- ASIC
- Integrated Circuit Design
- Embedded Software
- Static Timing Analysis
- Algorithms
- Semiconductors
- Microsoft Office
- CMOS
- R&d
- Semiconductor Design
- PowerPoint
- Microelectronics
- EDA
- Verilog
- System on a Chip Soc
- System on a Chip
- Integrated Circuits
- Very Large Scale Integration
- Application Specific Integrated Circuits
- Research and Development
Marcelo Jara Summary
- Marcelo Jara, based in State of São Paulo, Brazil, is currently a ASIC and SoC Physical Design and Timing Analysis Sr Technical Manag. at HCL Technologies. Marcelo Jara brings experience from previous roles at Instituto de Pesquisas Eldorado, State University of Campinas and Idea! Electronic Systems. Marcelo Jara holds a 1990 - 1996 PhD on EE, MSc on EE in Electrical Eng (FEE/DSIF), VLSI design, Parallel processing, Artificial Neural Networks @ Universidade Estadual de Campinas. With a robust skill set that includes Application Specific Integrated Circuits Asic, RTL design, Logic Synthesis, VLSI, Electronics and more. Marcelo Jara has 3 emails on RocketReach.
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