Marcello Giuffre' Email
Senior DFT Engineer @ Menta SAS
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Marcello Giuffre' Location
- Nice, FR
Marcello Giuffre' Work
- 2018 -now Senior DFT Engineer @
- 2016 -2018 DFT Lead @
- 2013 -2016 Co-Founder, DFT Lead @ Opal Design Systems
- 2009 -2013 Senior DFT Engineer in Omap Platform Bu @
- 2004 -2009 DFT Engineer in Ericsson Bu @
- 2003 -2003 Asic Engineer @
- 2002 -2003 Soc Designer @
- 2001 -2002 Design Engineer @
- 2000 -2001 Ip Designer @
- 2000 -2000 Validation Engineer @
- 1997 -1997 Analog Engineer @
- now Support Engineer @
- now Verification Engineer @
Marcello Giuffre' Education
- Polytechnic Institute of Turin
Masters (Electronics, Engineering, Communications)
1992-1999 - Institut SupRieure D'Electronique Du Nord 1996-1997
Marcello Giuffre' Skills
- DFT
- Scan Insertion
- ATPG
- BIST
- ASIC
- Static Timing Analysis
- Memory Test
- Simulation Modeling
- SoC
- Verilog
- RTL coding
- VHDL
- NCSim
- ModelSim
- JTAG
- Logic Synthesis
- IC
Marcello Giuffre' Summary
- Marcello Giuffre', based in Nice, FR, is currently a Senior DFT Engineer at Menta Sas. Marcello Giuffre' brings experience from previous roles at Silicon Mobility, Opal Design Systems and Texas Instruments. Marcello Giuffre' holds a 1992 - 1999 Masters in Electronics, Engineering, Communications @ Polytechnic Institute of Turin. With a robust skill set that includes DFT, Scan Insertion, ATPG, BIST, ASIC and more. Marcello Giuffre' has 4 emails on RocketReach.
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