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Marcel Lopes Location
Lund, SE
Marcel Lopes Work
2020 -now ASIC Developer @
2018 -2020 Hardware Engineer @
2017 -2018 Senior Verification Engineer @
2015 -2018 SoC Verification Engineer @
2010 -2015 SoC Verification Engineer @
2009 -2010 Digital IC Designer @
Marcel Lopes Education
UNICAMP - Universidade Estadual de Campinas
Lato Sensu (Clinical Engineer)
2011-2013
CI-BRASIl - CT2 2008-2008
Universidade Federal do Pará
Engineer's degree (Electrical Engineer)
2000-2007
Colégio Ideal
Marcel Lopes Skills
Test Engineering
Nexus Ieee Isto 5001
C
Nexus
Aurora 8B/10B Protocol
Debugging
System On A Chip Soc
Debussy/Verdi Debug Tools
Functional Verification
RTL design
Microprocessors
ASIC
VLSI
Verilog
Integrated Circuit Design
Microcontrollers
NCSim
Formal Verification
TCL
Simvision
Embedded Systems
CMOS
RTL coding
SoC
Microelectronics
EDA
SystemVerilog
Assembly
Semiconductors
Simulations
Physical Design
Static Timing Analysis
Soc Debug Architecture
Low Power Design
Very Large Scale Integration Vlsi
Verification
JTAG
Soc Functional Verification
Joint Test Action Group Jtag
IC
System on a Chip
Joint Test Action Group
Very Large Scale Integration
Marcel Lopes Summary
Marcel Lopes, based in Lund, SE, is currently a ASIC Developer at Ericsson. Marcel Lopes brings experience from previous roles at Cobham Gaisler, NXP Semiconductors and Freescale Semiconductor. Marcel Lopes holds a 2011 - 2013 Lato Sensu in Clinical Engineer @ UNICAMP - Universidade Estadual de Campinas. With a robust skill set that includes Test Engineering, Nexus Ieee Isto 5001, C, Nexus, Aurora 8B/10B Protocol and more. Marcel Lopes has 3 emails on RocketReach.
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