SOC Verification engineer| Counsltant @ (October 2024 - July 2025)
Staff Engineer @ (February 2023 - September 2024)
Senior Verification Engineer @ (January 2020 - January 2023)
Verification Engineer @ (July 2017 - January 2020)
SOC Verification Consultant @ (June 2021 - December 2022)
Consultant Design Verification Engineer @ (June 2019 - May 2021)
Consultant Design Verification engineer @ (October 2017 - May 2019)
VLSI design and verification course @ (March 2017 - June 2017)
Manu T Education
Acharya Institute Of Technology
BE - Bachelor of Engineering (Electrical and Electronics Engineering)
2013-2017
Manu T Skills
AXI
Application-Specific Integrated Circuits (ASIC)
Assertion Based Verification
Assertions
Code Coverage
Debugging
GLS
Gate Level Simulation
Perl
RTL Coding
RTL Design
RTL Verification
Scripting
System on a Chip (SoC)
Team Leadership
Team Management
Test Cases
Universal Verification Methodology (UVM)
VHDL
Verdi
Verilog
Very-Large-Scale Integration (VLSI)
system verilog
Manu T Summary
Manu T, based in Bengaluru, KA, IN, is currently a SOC and GLS Verification Engineer | Consultant at HrdWyr. Manu T brings experience from previous roles at Google, MaxLinear and FrenusTech Pvt Ltd. Manu T holds a 2013 - 2017 BE - Bachelor of Engineering in Electrical and Electronics Engineering @ Acharya Institute Of Technology. With a robust skill set that includes AXI, Application-Specific Integrated Circuits (ASIC), Assertion Based Verification, Assertions, Code Coverage and more. Manu T has 1 emails on RocketReach.
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