1994 -2000 Senior Design Engineer @ VLSI Technology, Inc.
Manoj Chandran Education
Arizona State University
Master of Science (M.S.) (Electrical and Electronics Engineering)
1992-1994
University of Madras
BE (Electrical and Electronics Engineering)
1987-1991
PSBB
Manoj Chandran Skills
Power
Prime Time
Synopsys
Micro And Macro Architecture
Several Successful Asic Designs From Spec To Gds
C
Experience Designing Large Soc'S And Mixed Signal Chips
RTL design
Sythesis
DFT
Verification At All Levels Block
System
Digital Design
Power Management
Verilog
Experience Managing Several Designers
VHDL
Place And Route Concepts And Flow
Bench/Lab
Debugging Customer Problems On Silicon
Semiconductors
Design
Static Timing Analysis
Mentor
Ets
Digital Competency Management And Mentorship
Cadence Tools
Chip
Verification
Verification at All Levels
Manoj Chandran Summary
Manoj Chandran, based in Chandler, AZ, US, is currently a Senior Logic Design Manager at Intel Corporation. Manoj Chandran brings experience from previous roles at Intel Corporation, IDT and NXP Semiconductors. Manoj Chandran holds a 1992 - 1994 Master of Science (M.S.) in Electrical and Electronics Engineering @ Arizona State University. With a robust skill set that includes Power, Prime Time, Synopsys, Micro And Macro Architecture, Several Successful Asic Designs From Spec To Gds and more. Manoj Chandran has 4 emails and 2 mobile phone numbers on RocketReach.
Looking for a different Manoj Chandran?
Find contact details for 700 million professionals.