NiosV CPU RTL Design Engineer @ (November 2022 - October 2024)
SoC Design Engineer @ (January 2016 - November 2022)
Advanced Design Engineer @ Altera (March 2015 - December 2015)
Design Engineering Intern @ Altera (June 2014 - December 2014)
Student Assistant @ (January 2014 - May 2014)
Teaching Assistant @ V.E.S Institute of Technology (July 2012 - April 2013)
General Secretary @ IEEE VIT (August 2011 - July 2012)
Mandar Raje Education
San Jose State University 2013-2015
Vidyalankar Institute of Technology 2009-2013
K.J Somaiya College of Science and Commerce 2007-2009
Chandrakant Patkar Vidyalaya,Dombivali 1998-2007
Mandar Raje Skills
CPU design
Analytical Skills
Communication
RTL Development
Debugging
Microarchitecture
Verilog
Xilinx ISE
Microcontrollers
Matlab
VHDL
ModelSim
Xilinx
Robotics
Event Management
Multisim
Proteus
Programming
Microprocessors
Microsoft Office
Pspice
VLSI
Atmel AVR
Keil
Cadence
C++
NI Multisim
Technology
Cadence Virtuoso
Solutions
SAN
CMOS
Altera
Semiconductors
Design
Architecture
Virtuoso
Technology Solutions
Mandar Raje Summary
Mandar Raje, based in San Jose, CA, US, is currently a RTL Design Engineer - Dojo at Tesla. Mandar Raje brings experience from previous roles at Intel Corporation and Altera. Mandar Raje holds a 2013 - 2015 San Jose State University. With a robust skill set that includes CPU design, Analytical Skills, Communication, RTL Development, Debugging and more. Mandar Raje has 3 emails and 1 mobile phone numbers on RocketReach.
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