Maithri Dinesh Email
Physical Design Engineer @ Synthara AG
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Maithri Dinesh Location
- Zürich, ZH, CH
Maithri Dinesh Work
- Physical Design Engineer @ (June 2024 - Present)
- DFT Design Engineer @ (July 2018 - May 2024)
- Intern @ (June 2017 - June 2018)
Maithri Dinesh Education
- Manipal School of Information Sciences
Master of Engineering (M.Eng.) (VLSI Design)
2016-2018 - St Joseph Engineering College
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
2011-2015 - Visvesvaraya Technological University
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
2011-2015
Maithri Dinesh Skills
- Automatic Test Pattern Generation (ATPG)
- BIST
- C
- DFT
- Low-power Design
- Perl
- Physical Design
- Python (Programming Language)
- Scan Insertion
- Shell Scripting
- System Verilog
- Tcl
- UPF
- Universal Verification Methodology (UVM)
- VHDL
- Verilog
- C++
- 8051 Microcontroller
- Matlab
- Awk
- Universal Verification Methodology Uvm
- Sed
- Universal Verification Methodology
Maithri Dinesh Summary
- Maithri Dinesh, based in Zürich, ZH, CH, is currently a Physical Design Engineer at Synthara AG. Maithri Dinesh brings experience from previous roles at Intel Corporation. Maithri Dinesh holds a 2016 - 2018 Master of Engineering (M.Eng.) in VLSI Design @ Manipal School of Information Sciences. With a robust skill set that includes Automatic Test Pattern Generation (ATPG), BIST, C, DFT, Low-power Design and more. Maithri Dinesh has 2 emails on RocketReach.
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