Ling Yang Email & Phone Number
Physical Design and Verification @ AMD
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Ling Yang Location
- San Jose, CA, US
Ling Yang Work
- Physical Design and Verification @ (February 2022 - Present)
- Design Engineer @ Xilinx Inc (July 2014 - October 2022)
- Design Engineer @ (September 2012 - June 2014)
- Principal SI and PI Engineer, SI and PI lead @ (May 2000 - September 2012)
Ling Yang Education
- University of Illinois Urbana-Champaign
MSEE (Electrical Engineer)
- Southeast University
Bachelor of Science (BS) (Electrical, Electronics and Communications Engineering)
Ling Yang Skills
- Power
- Signal Integrity
- Illustrator
- Interfaces
- Teaching
- PCB design
- Soc Ip Integration
- LIN
- Engineering
- Strategic Planning
- Physical Therapy
- Pdk
- Java
- SoC
- Power Integrity
- Simulation
- System And Chip Co Design
- Design
- Physical Design
- Power Tape Out Signoff
- On Chip Clock Delivery
- Clock Jitter Analysis
- Asic Design
Ling Yang Summary
- Ling Yang, based in San Jose, CA, US, is currently a Physical Design and Verification at AMD. Ling Yang brings experience from previous roles at Xilinx Inc, Samsung Semiconductor and Rambus Inc. Ling Yang holds a MSEE in Electrical Engineer @ University of Illinois Urbana-Champaign. With a robust skill set that includes Power, Signal Integrity, Illustrator, Interfaces, Teaching and more. Ling Yang has 3 emails and 1 mobile phone numbers on RocketReach.
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