Le Tran Email & Phone Number
Senior Layout Engineer @ Analog Devices
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Le Tran Location
- San Jose, CA, US
Le Tran Work
- 2007 -now Senior Layout Engineer @
- 1992 -2007 IC Layout Designer @ LATTICE SIMICONDUCOR
Le Tran Education
- Intergrate Circuit Mask Design Program, MOS Drafting Institute, SunnyVale, CA
ASEE , Electroinic Technology, Bay Valley Tech, Santa Clara, CA (Electrical and Electronics Analog/Digital Technologies)
1980-1982
Le Tran Skills
- Analog
- IC
- Mixsignal
- CMOS
- Power Management
- Silicon
- Analog Circuit Design
- FPGA
- ASIC
- Mixed Signal
- Semiconductors
- SoC
- EDA
- Cadence Virtuoso
- Integrated Circuit Design
- Circuit Design
- IC layout
- Integrated Circuit
Le Tran Summary
- Le Tran, based in San Jose, CA, US, is currently a Senior Layout Engineer at Analog Devices. Le Tran brings experience from previous roles at LATTICE SIMICONDUCOR. Le Tran holds a 1980 - 1982 ASEE , Electroinic Technology, Bay Valley Tech, Santa Clara, CA in Electrical and Electronics Analog/Digital Technologies @ Intergrate Circuit Mask Design Program, MOS Drafting Institute, SunnyVale, CA. With a robust skill set that includes Analog, IC, Mixsignal, CMOS, Power Management and more. Le Tran has 2 emails and 3 mobile phone numbers on RocketReach.
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