Lan Lin Location
- San Jose, CA, US
Lan Lin Work
- 2020 -now Sr. Design Engineer @
- 2020 -2020 Staff TD Module and Yield Engineer @
- 2016 -2020 TD Module and Yield Engineer @
- 2010 -2015 Research Assistant @
- 2006 -2009 Research Assistant @ Chinese Academy of Sciences
Lan Lin Education
- Penn State University
Doctor of Philosophy - PhD (Electrical Enginnering)
2010-2015 - University of Pittsburgh
(Electrical Engineering)
2009-2010 - Chinese Academy of Science
Master's degree (Optical Engineering)
2006-2009 - Zhejiang University
Bachelor's degree (Advanced Honor Class of Engineering Education (ACEE) in Chu Kochen Honor College)
2004-2006 - Zhejiang University
Bachelor (Optical Enginnering)
2002-2006
Lan Lin Summary
- Lan Lin, based in San Jose, CA, US, is currently a Sr. Design Engineer at ASML. Lan Lin brings experience from previous roles at Intel Corporation, Penn State University and Chinese Academy of Sciences. Lan Lin holds a 2010 - 2015 Doctor of Philosophy - PhD in Electrical Enginnering @ Penn State University. Lan Lin has 3 emails and 1 mobile phone numbers on RocketReach.
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