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Kit Cheong Location
Palo Alto, CA, US
Kit Cheong Work
Compiler development @ (August 2010 - Present)
Engineering Group Director @ (January 2002 - January 2009)
static timing analyzer project lead @ Silicon Perspective Corporation (January 1999 - January 2002)
MTS @ Bell Lab Design Automation/Cadence design systems (January 1997 - January 1999)
Digtal Simulation and Analysis team lead @ Rockwell Semiconductor Systems, Newport Beach CA (January 1996 - January 1997)
MTS @ AT&T Bell Labs, Murray Hill, NJ (January 1986 - January 1995)
Kit Cheong Education
University of Minnesota
BS (Mathematics and Computer Science)
University of Minnesota
MS (Computer Science)
Kit Cheong Skills
Leadership
Development
PowerPoint
Linux
Algorithms
C
Debugging
Windows
Perl
ASIC
Verilog
Integrated Circuit Design
Engineering
Cadence
TCL
Embedded Systems
Microsoft Excel
SoC
EDA
Scalability
Semiconductors
Design
Static Timing Analysis
Software Development
Patents
R&D
Prototyping
Kit Cheong Summary
Kit Cheong, based in Palo Alto, CA, US, is currently a Compiler development at Vivante Corporation. Kit Cheong brings experience from previous roles at Cadence Design Systems, Silicon Perspective Corporation, Bell Lab Design Automation/Cadence design systems and Rockwell Semiconductor Systems, Newport Beach CA. Kit Cheong holds a BS in Mathematics and Computer Science @ University of Minnesota. With a robust skill set that includes Leadership, Development, PowerPoint, Linux, Algorithms and more. Kit Cheong has 2 emails and 3 mobile phone numbers on RocketReach.
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